AD9640ABCPZ-150

Product Summary

The AD9640ABCPZ-150 is a dual 14-Bit 150 MSPS analog-to-digital converter. The D9640ABCPZ-150 is designed to support communications applications where low cost, small size, and versatility are desired. The dual ADC core features a multistage differential pipelined architecture with integrated output error correction logic. The D9640ABCPZ-150 features wide bandwidth differential sample-and-hold analog input amplifiers supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compen-sate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance. The applications of the AD9640ABCPZ-150 include Communications, Diversity radio systems, Multimode digital receivers: GSM, EDGE, PHS, UMTS, WCDMA, CDMA-ONE, IS95, CDMA2000, IMT-2000, WiMax, I/Q demodulation systems, Smart antenna systems, General-purpose software radios, Broadband data applications.

Parametrics

AD9640ABCPZ-150 absolute maximum ratings: (1)AVDD, DVDD to AGND: -0.3 V to +2.0 V; (2)DRVDD to DRGND: -0.3 V to +3.9 V; (3)AGND to DRGND: -0.3 V to +0.3 V; (4)VIN+A/B, VIN-A/B to AGND: -0.3 V to AVDD + 0.2 V; (5)CSB to AGND: -0.3 V to +3.9V; (6)D0A/B through D13A/B to DRGND: -0.3 V to DRVDD + 0.3 V; (7)FD0A/B through FD3A/B to DRGND: -0.3 V to DRVDD + 0.3 V; (8)DCOA/B to DRGND: -0.3 V to DRVDD + 0.3 V; (9)VREF to AGND: -0.3 V to AVDD + 0.3 V; (10)SENSE to AGND: -0.3 V to AVDD + 0.2 V; (11)Operating Temperature Range (Ambient): -40℃ to +85℃; (12)Maximum Junction Temperature Under Bias: 150℃; (13)Storage Temperature Range (Ambient): -65℃to +150℃.

Features

AD9640ABCPZ-150 features: (1)SNR = 71.7 dBc (72.7dBFS) to 70 MHz @ 150 MSPS; (2)SFDR = 85 dBc to 70 MHz @ 150 MSPS; (3)Low Power: 780 mW; (4)1.8V analog supply operation; (5)1.8V to 3.3V CMOS output supply or 1.8V LVDS supply; (6)Integer 1 to 8 Input Clock Divider; (7)IF sampling frequencies to 450 MHz; (8)Internal ADC voltage reference; (9)Integrated ADC sample-and-hold inputs; (10)Flexible analog input: 1 V p-p to 2 V p-p range; (11)Differential analog inputs with 650MHz bandwidth; (12)ADC clock duty cycle stabilizer; (13)95 dB channel isolation/crosstalk; (14)Serial Port Control; (15)User-configurable built-in self-test (BIST) capability; (16)Energy-saving power-down modes; (17)Integrated Receive Features: Fast Detect/Threshold Bits; Composite Signal monitor.

Diagrams